The present invention relates in general to data transmission between the switching systems of a telecommunications network and more particularly to an addressing and memory circuit for accessing and storing control data messages in a remote data link controller.
In modern digital telecommunication switching systems a concept of network modularity has been designed allowing the interconnection of small switching systems remote to a larger host system. These remote switching systems have capacities to handle between a few hundred and a few thousand telephone subscribers. The remote switching systems are normally used in areas where the installation of a large switching system would be uneconomical.
A high speed digital data link typically interfaces the host switching system to the remote system through which large amounts of voice and control data are exchanged. The voice data normally comprises subscriber calls switched through either the host or the remote system. The control data may be status exchanges between the host and the remote, i.e. centralized administration, billing and maintenance, or the direct control of the operation of the remote by the host.
The control data exchanges are originated in the sending system peripheral processor transmitted over the high speed digital data link to the receiving system peripheral processor where the data is interpreted. In order to relieve each peripheral processor from the burden of controlling the data link a remote data link controller is implemented in each system which performs all tasks involved in the formatting, transmission and reception of the control data.
The remote data link controllers are connected to each other via digital spans. The digital spans may be T1, T2 or T1C, T3 carriers using DS1, DS2 or DS1C, DS3 data formats, respectively. These digital spans transmit data at high speeds serially at a rate of approximately 1.5-45 megabits per second.
Typically, the transmitting peripheral processor outputs data words to the link controller where the data words are assembled or formatted into a data message or packet. The packet is then transmitted to the receiving link controller where the data message is reformatted back into data words readable by the receiving peripheral processor.
In cases where more than one remote switching system is connected to a host switching system a dedicated data link controller for each data link is normally required. Therefore, if 16 remote units are connected to a host then 16 link controllers would be required to control 16 data links.
It is more economically advantageous however, to be able to control all data links with only one controller. The multiple link remote data link controller would service each data link in a sequential fashion processing the control data for a set amount of time for each link before going on to the next. Formatted data messages are stored away in a temporary memory or scratch pad memory and at the appropriate time in the servicing sequence would be output to the link. Similarly, receive control messages are read into the scratch pad memory and at the appropriate time in the servicing sequence are transferred to the reformatting circuit of the controller for processing.
Accordingly, it is the object of the present invention, to provide an address sequencer and memory circuit for use in a multiple link remote data link controller.